Virtually Splitting Data Caches using Multiple Address Decoders

An address decoder is a small hardware unit that uses an address to index and place the data into memory units including cache memories. In current CPU cache designs there is a single decoder unit which serves to place data into the cache. In this paper we describe a technique to reduce contention on CPU’s caches through the use of multiple address decoders. We argue that by using multiple decoding techniques better data placement can be achieved and the CPU cache can be better utilized. We present an overview of an instrumentation tool developed to collect fine-grained data traces and a technique for virtually splitting caches using separate address decoders. Our results demonstrate the feasibility and the impact of virtual cache splitting.